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This board was designed as a silicon validation platform for the STx7111. As such it is socketed and has a large array of connectors and jumpers. Hardware SetupSwitch settingsThe boards normally ship with the jumpers set so that the serial ports are disabled. To enable them ensure that J1 and J2 are in the 1-2 position. Serial ports
Memory ConfigThe mb618 is the first board which is only supported through target packs rather than gdb stdcmd files. st40load_gdb is still used to boot targets using a target pack, but the name (or IP address) of the target and the board connection procedure are now combined into a single TargetString. The TargetString has the form: <stmc_name>:<target_pack>[:<core_name>][,parameter=value...] where:
For example: st40load_gdb -t 10.1.2.3:mb618:st40,seuc=1,silent=1 -b vmlinux For further details of target packs see the documentation provided with the stmc package, which is normally installed in: /opt/STM/STLinux-2.3/host/stmc/doc/targetpack.pdf
GMACTo use the embedded GMAC on board you need to have the following setup:
Note 1: GMAC only works in MII mode Note 2: PHY on board is SMSC LAN8700 MDIO and U-boot's mii info commandRegarding the Serial Management Interface (SMI) (i.e. the MDIO and MDC signals), the normal convention is a pull-UP resistor is connected to the open-collector/drain MDIO signal. Thus, if for a given address, there is no PHY physically connected, then the MDIO will always be 1. That is, reading data of 0xffff, indicates a "missing device". However, on the MB618, MII_MDIO pin is connected to MODE[0], and may be pulled either UP or DOWN, depending on SW11-2. If SW11-2 is ON, then a pull-DOWN resistor used.
If SW11-2 is OFF, then a pull-UP resistor used.
Note: changing MODE[0], will affect the reference clock selection for ClockGenA, during power-on. This may have an adverse affect on the system. Please ensure you know what you are doing if you change SW11-2. EPLDAn EPLD with version 04 programming is required to use the GMAC. So far it appears as if rev B boards were shipped with version 03 EPLD programming, and so will need to be upgraded. Occasionally with the version 04 EPLD the PHY will not be reset correctly. In this case it will be necessary to perform a manual reset. With the board powered on, set SW7-4 ON, press the reset button on the front pannel (SW6), and then set SW7-4 OFF again. It should only be necessary to do this once after powering on the board. The version 05 EPLD controls the PHY reset in software, and so must only be used with kernel version 2.6.23.16_stm23_0108 or later. To enable software control of the PHY, SW7-4 must be ON. PatchesPatches are available here for early adoptors. These are against the 2.6.23.13 kernel.
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