Performance counters are an ST40 hardware feature to aid the debugging and analysis of an application, by providing the ability to count execution cycles or the occurrences of several different kinds of events during the execution of an application.
The ST40 provides a pair of 48-bit counters, designated as counter1 and counter2. These counters can be configured to count the occurrence of a variety of useful events, or to count cycles while the ST40 core is in certain states.
The counters can be either started and stopped manually from GDB or automatically by specifying start and stop triggering addresses, which when the instructions at these addresses are executed, start and stop the counters.
Each counter can be individually configured to start and stop automatically at these triggering addresses. However, the ST40 only supports a single pair of start and stop trigger addresses which are shared between both performance counters. As a consequence, both counters start and stop at the same triggering addresses.
The counters can be individually configured to count any one of the 34 different events or states listed in Performance Counter Modes, where the type of event or state is identified by either its numeric code or its corresponding symbolic name (which is a mnemonic for the event).
The counter modes in which the counter counts in cycles instead of discrete events, support the following two forms of cycle counting:
The performance counters do not have any impact on CPU performance.
The performance counter features are accessible though the GDB perfcount command.