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Networking and Ethernet devices |
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Stb7109 STMMAC 10/100 Ethernet
The STx7109 has an integrated ethernet controller and MAC processor.
It includes an MII/RMII port for connection to an external PHY controller.
The STb7109 Ethernet subsystem is composed of three main layers (Synopsys - DesignWare Ethernet MAC 10/100):
- DMA
- Transaction Layer Interface (TLI)
- Media Access Controller (MAC)
The on-chip Ethernet controller includes a MAC function which connects to an external Physical layer controller via IEEE 802.3 standard Media Independent Interface (MII) I/O pins.
The MII is used for transmitting and receiving the Ethernet data payload to and from the PHY, as well as passing configuration information such as when the connection changes between 10 and 100 Mbit/s and half-duplex or full-duplex operation.
The STe101P PHY (available as a db666 daughter card for the MB411) provides a means of implementing and validating a type MII or RMII Ethernet interface on the MB411.
The Reduced Media Independent Interface (RMII) provides a low cost alternative to the IEEE 802.3u MII interface.
Kernel configuration
The kernel configuration option is STMMAC_ETH:
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Device Drivers --->Network device support--->Ethernet (10 or 100MBit)---> STM MAC Ethernet driver
The
DMA_RX_SIZEandDMA_TX_SIZEare the max number of descriptors in the DMA RX/TX linked lists.The
STMMAC_DEBUGoption enables the debug mode for the IRQ handle.The
STMMAC_NAPIoption enables the NAPI support.Note: NAPI is a new driver API designed to reduce CPU and interrupt load when the driver is receiving lots of packets from the card.
The
STMMAC_EXT_CLKenables the PHY external clock for the RMII mode.
Configuring the STe10xp physical interface
Note: in this distribution the STe10Xp devices are supported using the new PHY Abstraction Layer technology.
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Device Drivers --->Network device support---> PHY device support---> PHY Device support and infrastructure ---> Driver for STM STe10Xp--->
The CONFIG_PHY_MII selects the Media Independent Interface (MII).
The CONFIG_PHY_RMII selects the Reduced Media Independent Interface (RMII).
Command line option
stmmaceth=msglvl:<
debug_msg_level>
,phyaddr:<
phy_address>
,watchdog:<
watchdog>
,rxsize:<
min_rx_pkt_size>
where:
<debug_msg_level>: message level (0: no output, 16: all)<phy_address>: physical device address<watchdog>: transmit timeout (in milliseconds)<min_rx_pkt_size>: copy only tiny-frames for the incoming frame. It should be used for tuning the zero-copy level for the reception process.
Note: the module parameters can be found in the sysfs virtual filesystem:
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For example, the following command modifies the transmit timeout:
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Kernel configuration
The kernel configuration options are CONFIG_STB7109_ETH and CONFIG_STE101P:
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Device Drivers --->Networking Support --->Network device support--->Ethernet (10 or 100MBit)---> STb7109 Ethernet driver (EXPERIMENTAL)
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Device Drivers ---> Networking Support ---> Network device support---> PHY device support---> PHY Device support and infrastructure---> Drivers for STe101p (EXPERIMENTAL)
Command line options
<ethx>: is the ethernet device name (by default the "eth0" will be used)<phy_n>: STe101p PHY device address, by default the driver is able to detect it automatically<flowctrl>: enable/disable the flow-control [0|1]
stb7109eth=<msg_level>,<watchdog>,<pause_time>
ste101p=device:<ethx>,addr:<phy_n>,flowctrl:<flowctrl>
where:
Notes
- MAC address must be provided by using nwhwconf support;
- Virtual LAN (VLAN) support is available but not fully tested;
- No Flow-control;
- The netpoll support is not fully tested;
- The PHY driver doesn't support the SMII mode yet (note that the SMII interface is only available in STe101p PHY);
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using the db666 (both in RMII and MII mode) with the clock through the STPIO3 pin 7, you need to modify the PLL1 clock. The following patch file changes the PLL1 clock from384 MHz to 400 MHz in the /opt/STM/ST40R3.0.3/sh-superh-elf/stdcmd/mb411stb7109.cmd file;
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Using the db666 in RMII mode, if the clock (50 MHz) is supplied using an external device (clock generator), the following scenarios are available:
The
STMMAC_EXT_CLKoption in the Kernel is set (SYS_CFG7[19]=1): the STPIO3 pin 7 is configured as input. You should connect the external clock generator to both the PHY card and the STPIO3 pin 7.The
STMMAC_EXT_CLKoption is not set (SYS_CFG7[19]=0): the STPIO3 pin 7 is configured as output. You need to connect the external clock generator to the PHY card.
- On the mb411 board the 7109 Ethernet driver and the smc91x driver are mutually exclusive.
On the mb442 board the SMSC91C111 fully works if, in the mb442stb7109cut30.cmd command file, the
EMI_BANK0_EMICONFIGDATA1is set to 0x9d200000.-
Concerning the 7109 Ethernet interface, the mb442 board uses the Ste100p PHY.
The Ste100p only supports the MII mode. For boards with 30MHz crystals, in the command file, the
stb7100_set_clockgen_a_pll1must be set to 0x1e 0xc8 0x0.
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Last updated: 2008/06/27 07:18:21
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